This application claims the benefit of Korean Patent Application No. 2000-70039, filed on Nov. 23, 2000, under 35 U.S.C. xc2xa7119, the disclosures of which are incorporated by reference herein in their entirety.
1. Field of the Invention
The invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a method of identifying programmed defective addresses thereof.
2. Description of Related Art
Typically, semiconductor memory device are manufactured with redundant memory cells to replace defective memory cells identified during the manufacturing process, thereby improving manufacturing yield.
The memory cell array of a typical semiconductor memory device will generally comprise a plurality of memory cell array blocks each containing normal memory cell array blocks and redundant memory cell array blocks. When a defective memory cell is found in the memory cell array block, the address of the defective memory cell is programmed to access a redundant memory cell instead of the defective one, usually by use of a fuse circuit, wherein fuses representing individual bits are cut by laser as needed to divert the data bus to read and write to the redundant cell.
However, even though defective memory cells may be detected and replaced at the wafer-level of manufacture, defective memory cell arrays are still occasionally found later at the package level. Of defects at the package level, more than about 80% comes from failure of no more than one or two 1-bit or 2-bit memory cells. Thus, if the defective memory cells of 1-bit or 2-bit can be repaired, manufacturing yield of semiconductor memory devices can be significantly improved. To correct the problem at the package level, typical semiconductor memory devices also comprise a redundant fuse circuit to repair the defective memory cells at a package level. Such redundant fuse circuits program defective addresses not by laser-blowing a fuse directly, but by electrically blowing an electrical fuse.
However, because the redundant fuse program circuit performs its program operation at a package level, it cannot be externally observed whether defective addresses are exactly programmed or not or whether the redundant fuse program circuit is in use.
Disclosed is a semiconductor memory device comprising a memory cell array comprising a plurality of memory cells, a plurality of redundant fuse program circuits adapted to program a redundant control signal and a defective address of a defective memory cell among the plurality of the memory cells at a package level in response to a first control signal and an address signal applied from an external portion and generate a comparison coincident signal in response to the redundant control signal when the address is consistent with the defective address and outputting the comparison coincident signal to an external portion in response to a second control signal during a test operation, and a mode setting register adapted to set a state of the first and second control signals in response to a command signal and a mode setting signal applied from an external portion.
In another aspect of the invention, a signal output circuit is adapted to receive a redundant control signal from said fuse program circuit outputted by said fuse program circuit in response to the second control signal.
In another aspect of the invention, the mode setting register is adapted to set a state of the first control signal, a test mode signal, and a normal mode signal in response to the command signal and the mode setting signal during a test operation at a package level; and further comprises a control signal generating circuit adapted to generate a signal applied from an external portion in response to the test mode signal as the second control signal and disabling the second control signal in response to the normal mode signal.
In another aspect of the invention, the control signal generating circuit comprises a CMOS transmission gate for transmitting the signal applied from the external portion in response to the test mode signal, a first latch for inverting and latching an output signal of the CMOS transmission gate, an inverter for inverting an output signal of the first latch to generate the second control signal, and a reset transistor for resetting the second control signal in response to the normal mode signal.
In another aspect of the invention, the redundant fuse program circuit comprises a redundant control signal generating circuit for generating a redundant control signal in response to the first control signal, and a defective address programming circuit for receiving the address in response to the first control signal to program a fuse, so that the defective address is programmed.
In another aspect of the invention, the redundant control signal generating circuit comprises a first fuse connected between a power voltage and a first node, a first NMOS transistor serially connected between the first node and a ground voltage and receiving the address and the first control signal, and a second latch for inverting and latching an output signal of the first node to be outputted.
In another aspect of the invention, the defective address programming circuit comprises a second fuse connected between a power voltage and a second node, second and third NMOS transistors serially connected between the second node and a ground voltage and receiving the address and the first control signal, and a third latch for inverting and latching an output signal of the second node to be outputted.
In another aspect of the invention, a data output buffer for buffering and outputting a signal outputted from the signal output circuit to an external portion during a test operation.
Disclosed is a memory cell array comprising a plurality of memory cells, a defective address programming means for programming a redundant control signal and a defective address of a defective memory cell among the plurality of the memory cells at a package level in response to a first control signal and an address signal applied from an external portion, an output means for outputting the defective address outputted from the defective address programming means to an external portion in response to a second control signal during a test operation, and a mode control signal setting means for setting a state of the first and second control signals in response to a command signal and a mode setting signal applied from an external portion.
In another aspect of the invention, the output means further outputs the redundant control signal in response to the second control signal.
In another aspect of the invention, the mode control signal setting means comprises a mode setting register for setting a state of the first control signal, a test mode signal and a normal mode signal in response to the command signal and the mode setting signal during a test operation at a package level, a control signal generating means for generating a signal applied from an external portion in response to the test mode signal as the second control signal and disabling the second control signal in response to the normal mode signal.
In another aspect of the invention, the control signal generating means comprises a CMOS transmission gate for transmitting the signal applied form the external portion in response to the test mode signal, a first latch for inverting and latching an output signal of the CMOS transmission gate, an inverter for inverting an output signal of the first latch to generate the second control signal, and a reset transistor for resetting the second control signal in response to the normal mode signal.
In another aspect of the invention, the defective address programming means comprises a redundant control signal generating circuit for generating a redundant control signal in response to the first control signal, and a defective address programming circuit for receiving the address in response to the first control signal to program a fuse, so that the defective address is programmed.
In another aspect of the invention, the redundant control signal generating circuit comprises a first fuse connected between a power voltage and a first node, a first NMOS transistor serially connected between the first node and a ground voltage and receiving the address and the first control signal, and a second latch for inverting and latching an output signal of the first node to be outputted.
In another aspect of the invention, the defective address programming circuit comprises a second fuse connected between a power voltage and a second node, second and third NMOS transistors serially connected between the second node and a ground voltage and receiving the address and the first control signal, and a third latch for inverting and latching an output signal of the second node to be outputted.
In another aspect of the invention, the output means comprises a signal output means for outputting the redundant control signal and the defective address in response to the second control signal, and a data output buffer for buffering and outputting a signal outputted from the signal output circuit to an external portion during a test operation.
Disclosed is a method of identifying a programmed defective address in a semiconductor memory device having a memory cell array comprising a plurality of memory cells and a defective address programming means for programming a defective address of a defective memory cell among the plurality of the memory cells at a package level in response to a first control signal and an address signal applied from an external portion, the method comprising generating a first control signal in response to a command signal and a mode setting signal applied from an external portion, programming the defective address programming means in response to the first control signal and a defective address applied from an external portion to generate a redundant control signal and a defective address, generating a second control signal in response to the command signal and the mode setting signal, and outputting a comparison coincident signal to an external portion in response to the second control signal when an address applied from an external portion is consistent with the defective address.
In another aspect of the invention, the method further comprises outputting the redundant control signal to an external portion in response to the second control signal.
Disclosed is a method of identifying a programmed defective address in a semiconductor memory device having a memory cell array comprising a plurality of memory cells and a defective address programming means for programming a defective address of a defective memory cell among the plurality of the memory cells at a package level in response to a first control signal and an address signal applied from an external portion, the method comprising generating a first control signal in response to a command signal and a mode setting signal applied from an external portion, programming the defective address programming means in response to the first control signal and a defective address applied from an external portion to generate a redundant control signal and a defective address, generating a second control signal in response to the command signal and the mode setting signal, and outputting the defective address to an external portion in response to the second control signal.
In another aspect of the invention, the method further comprises outputting the redundant control signal to an external portion in response to the second control signal.